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1. 媛� ���

��� 媛���곌린 ��ㅺ��瑜� ��듯�� ���諛������� Modelsim, Xilinx ISE ��ъ�⑸�� ��ㅼ��
��� TEST bench, simulation 諛⑸�� ��댄��

2. 臾� ���

(1) 3*8 Decoder

-Behavioral modeling
library ieee;
use ieee.std_logic_1164.all;
entity decoder is
port (x : in std_logic_vector(2 downto 0);
d : out std_logic_vector(7 downto 0));
end decoder;
architecture behavioral of decoder is
begin
process (x)
begin
case x is
when 000 ���] d [��� 10000000 ;
when 001 ���] d [��� xxx00000 ;
when xxx ���] d [��� 0xxx0000 ;
when xxx ���] d [��� 00xxx000 ;
when 100 ���] d [��� 000xxx00 ;
when 101 ���] d [��� 0000xxx0 ;
when 110 ���] d [��� 00000xxx ;
when others ���] d [��� 00000001 ;
end case;
end process;
end behavioral;
-Data flow modeling
library ieee;
use ieee.std_logic_1164.all;
entity decoder_dataflow is
port( x: in std_logic_vector(2 downto 0);
d: out���(������)

d(2) [��� not x(0) and x(1) and not x(2);

d(3) [��� x(0) and x(1) and not x(2);

d(4) [��� not x(0) and not x(1) and x(2);

d(5) [��� x(0) and not x(1) and x(2);

d(6) [��� not x(0) and x(1) and x(2);

d(7) [��� x(0) and x(1) and x(2);